1. Field of the Invention
The invention relates generally to a semiconductor devices, semiconductor dies, and a related method of processing a semiconductor wafer. More particularly, the invention relates to a semiconductor die incorporating one or more protective layer(s) having improved step coverage amongst other benefits. The invention also relates to a method of processing a semiconductor wafer to manufacture the semiconductor die incorporating the improved protective layer.
A claim of priority has been made to Korean Patent Application No. 10-2004-0077733 filed on Sep. 30, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Contemporary semiconductor manufacturing processes typically produce multiple integrated circuit chips (or dies) on a single semiconductor wafer. The peripheral boundaries separating individual dies are marked or defined by scribe lines formed (e.g., inscribed) in the surface of the semiconductor wafer. Scribe lines have many useful purposes. For example, once the complicated sequence of processing steps forming the plurality of dies is complete, individual die, or groups of die, may be accurately cut from the semiconductor wafer using a diamond-tipped cutter that follows a path defined by scribe lines.
Consider, for example, the partial view of a conventional semiconductor die shown in Figure (FIG.) 1. Of note, the conventional die includes a protective layer covering (or intended to cover) peripheral portions of a substrate and multi-layer structure formed on the substrate as part of the conventional die. A scribe line (SL) is located in the recess region.
The conventional die shown in FIG. 1 shows two exemplary multilayer structures, each comprising a conductive line 18 electrically connected to a conductive region 12 formed on substrate 10. (Throughout this description the term “on” is used to describe a spatial relationship between layers, components and/or elements. The term “on” may be used to describe a relationship where “A is directly on B,” or a relationship where “A is on B,” but one or more intervening layers, components and/or elements separate A from B. See, e.g., the relationship between conductive line 18 and substrate 10).
The multilayer structures shown in FIG. 1 are separated by the scribe line (SL). Conductive line 18 is connected to conductive region 12 via a contact plug 16 formed in a first interlayer insulator 14. A protective layer 22 is formed over the multilayer structure to cover an upper surface of a second interlayer insulator 20 formed on conductive line 18, as well as the side surfaces of first and second interlayer insulators 14 and 20.
In this manner the constituent parts of the multilayer structures are intended to be protected by protective layer 22 from the potentially harmful effects of the ambient environment. For example, protective layer 22 absorbs impacts likely to occur during subsequent processing of the semiconductor wafer containing the individual die. Packaging processes are an excellent example of these subsequent processes.
In order to optimize its impact-absorbing an other protective qualities associated with protective layer 22, the layer must remain firmly attached (adhered) to the upper surface of second interlayer insulator 20, the side surfaces of the first and second interlayer insulators 14 and 20, and at least some portion of the upper surface of substrate 10 around the scribe line (SL). Unfortunately, the large and steep step formed by the side surfaces of first interlayer insulator 14 and second interlayer insulator 20, make adhesion by protective layer 22 difficult. This problem is particularly pronounced at the intersections of horizontal and vertical surfaces. Note the lifting phenomenon indicated in section “a” of FIG. 1. Note also the uncovered, upper corner portion of second interlayer insulator 20 indicated in section “b” of FIG. 1.
When coverage by protective layer 22 is incomplete, impacts occurring during subsequent processing may cause cracking or fracture of fragile portions of the multi-layer structures formed on substrate 10. For example, when inadequate coverage by protective layer 22 results in a diminished impact-absorbing capacity, first interlayer insulator 14 and/or second interlayer insulator 20 may crack during attachment of a lead frame to the semiconductor die. The exposed edge corner of second interlayer insulator 20 is particularly susceptible to impact damage.
Additionally, when protective layer 22 begins to lift or otherwise becomes separated from the underlying layers of the multiplayer structure, chemicals, moisture, or other contaminates may infiltrate the multilayer structure during subsequent processing, such as a KOH reliability measurement, a pressure cooker test, etc.
As a result of the these potentially detrimental effects, the improved adhesion and step coverage of protective layer 22 has been the subject of significant research. For example, U.S. Pat. No. 5,300,816 is directed to a method of improving the step coverage for a similar protective layer.
FIG. 2 generally illustrates one embodiment of the method described in U.S. Pat. No. 5,300,816. Referring to FIG. 2, a multilayer structure (MS) is formed on a semiconductor substrate 50 having a device isolation layer 52. A scribe line (SL) separates adjacent multilayer structures. Each multilayer structure (MS) comprises five layers consecutively numbered in the figure as 61 through 65 with the bottommost layer being designated 61 and the uppermost layer being designated 65. In the illustrated example, individual layers 61, 63, and 65 are conductive layers, and individual layers 62 and 64 are insulators.
Note that each successively lower layer extends laterally towards the periphery of the multilayer structure by a greater distance. In this manner, each one of individual layers 61 through 65 is a bit longer than the layers disposed above it. Thus, the length of insulating layer 64 is a distance L2 longer than the length L1 of conductive layer 65. As a result, the edge portion of the multilayer structure (MS) formed by the combination the individual layers 61 through 65 takes on the form of a stepped incline, rather than the steep vertical drop shown in FIG. 1. This stepped incline allows improved protection layer coverage.
Unfortunately, the manufacturing process adapted to produce the multilayer structure (MS) illustrated in FIG. 2 is overly complex due to the multiple deposition and photolithography processes required to form the plurality of individual layers of varying length. This is particularly true where alignment (or other spatial relationships) between conductive layers 61, 63, and 65 and insulators 62 and 64 must be precisely controlled. Of further note, the multilayer structure (MS) illustrated in FIG. 2 contributes to an undesirable increase in overall die size.